--test1.e

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import vv_ahblite_config;
import e/vv_ahblite_master_seq_lib;

-- *************************************************************************
-- IVB-NOTE : REQUIRED : Test body : 09 Example - test 
-- -------------------------------------------------------------------------
-- The following example test scenario checks a read-after-write bus behavior
-- using the READ_AFTER_WRITE sequence (defined in the
-- vv_ahblite_master_seq_lib file).
-- Each master generates a random number between [0..8] of WRITE 
-- transaction, each followed by a READ transaction.
-- Use this section to define a test example for your UVC.
-- To do so edit the following example: 
 
-- Create a sequence for M0

extend M0 MAIN vv_ahblite_master_sequence {
    
    !wrseq : BASIC_WRITE vv_ahblite_master_sequence;
    !rdseq : BASIC_READ vv_ahblite_master_sequence;
    
    !wrap4 : WRAP4_RW vv_ahblite_master_sequence;
    !wrap8 : WRAP8_RW vv_ahblite_master_sequence;
    !wrap16 : WRAP16_RW vv_ahblite_master_sequence;
    
    !incr4 : INCR4_RW vv_ahblite_master_sequence;
    !incr8 : INCR8_RW vv_ahblite_master_sequence;
    !incr16 : INCR16_RW vv_ahblite_master_sequence;
    
    !incr : INCR_RW vv_ahblite_master_sequence;
//    !problem: PROBLEM_SEQ vv_ahblite_master_sequence;
     !busy_after_idle : PROB_BUSY_AFTER_IDLE vv_ahblite_master_sequence;
    
    num : uint;
       keep num in [1..8];
           
    body() @driver.clock is only {
    	for i from 1 to num do {
    		do wrseq;
            do rdseq;
            do wrap4 keeping{
            	.busy == i-1;
            	.start_address == 0x34;
            	.write == i%2;
            };
            
            --do busy_after_idle;
            
            
            --var data: list of byte;
            --data = single_read(0x2000, INCR4, NONSEQ, WORD);
            --data = single_read(0x2004, INCR4, SEQ, WORD);
            --data = single_read(0x2008, INCR4, BUSY, WORD);
            --data = single_read(0x2008, INCR4, SEQ, WORD);
            --data = single_read(0x200C, INCR4, SEQ, WORD);
            
            
//            do problem;
            do incr4 keeping{
            	.busy == i-1;	
            	.start_address == 0x0FC;
            	.write == i%2;
           };
            
           do wrap8 keeping{
            	.busy == i-1;
            	.start_address == 0x34;
            	.write == i%2;
            };
           
           do wrap16 keeping{
            	.busy == i-1;
            	.start_address == 0x42;
            	.data_size == HALFWORD;
            	.write == i%2;
            };
           
           do incr keeping{
            	.busy == i-1;
            	.start_address == 0x20;
            	.write == i%2;
            };
           
           do wrap4 keeping{
            	.busy == 0;
            	.data_size == WORD;
            	.start_address == 0x2C;
            	.write == i%2;
            };
           
           do incr8 keeping{
            	.busy == i-1;	
            	.start_address == 0x100;
            	.write == i%2;
           };
           
           do incr16 keeping{
            	.busy == i-1;	
            	.start_address == 0x120;
            	.write == i%2;
           };
           
           
    	};
    }; 
    
    --body() @driver.clock is only {
        
    --    message(LOW , "USAO U M) MAIN SEQUENCE!");
    --    
       --   do my_transaction keeping {
     ---       .addr == 0xffffffff;
      --      .burst == SINGLE;
       --     .lock == 0;
     --       .protect == 0;
      --      .data_size == BYTE;
     ----       .transfer == NONSEQ;
      --      .write_op == 1;
       --     .write_data[0] == 0xff;
       --     .transaction_kind == MASTER;
       -- };;
        
    --};
}; 

-- *************************************************************************

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